(1) Field of the Invention
The present invention relates to a static memory circuit, more particularly, to a static memory circuit which ensures high speed operation without data destruction by resetting a pair of bit lines to an equivalent potential before a change of an input address signal.
(2) Description of the Prior Art
Recently, to ensure an accurate reading operation in a memory circuit, a technique has been employed in which, before accessing a memory cell, a pair of bit lines are reset to a predetermined level, such as an intermediate level between a high (H) level and a low (L) level. This shortens the transition time of the bit-line potentials to the desired H level or the L level during a reading operation. In this technique, the bit-line potentials must be completely reset before raising the potential of the selected word line.
In a conventional static memory circuit, the reset of a bit-line potential is carried out immediately after the change of an input address signal, as described later in detail. However, improvements in high speed operation of static memory circuits have increasingly shortened the period from when the input address signal changes to when the potential of the word line rises, i.e., an output of a decoder. Because of this, the potential of the word line often rises before completion of resetting the bit-line potentials. Thus, data stored in the memory cell connected to the selected pair of bit lines is often destroyed, or the reading operation is often delayed.